1. Field of the Invention
The present invention relates to an apparatus and a method for providing a heat sink on a semiconductor chip. More particularly, the present invention relates to forming a heat sink on an upper surface of a semiconductor chip by placing a heat conductive material thereon which forms a portion of a glob top.
2. State of the Art
Chip On Board ("COB") techniques are used to attach semiconductor dice to a printed circuit board including flip chip attachment wirebonding and tape automated bonding ("TAB").
Flip chip attachment consists of attaching a flip chip to a printed circuit board or other substrate. A flip chip is a semiconductor chip that has a pattern or array of terminations spaced around an active surface of the flip chip for face down mounting of the flip chip to a substrate. Generally the flip chip active surface has one of the following electrical connectors: Ball Grid Array ("BGA")--wherein an array of minute solder balls is disposed on the surface of a flip chip which attaches to the substrate ("the attachment surface"); Slightly Larger than Integrated Circuit Carrier ("SLICC")--which is similar to a BGA but has a smaller solder ball pitch and diameter than a BGA; or a Pin Grid Array ("PGA")--wherein an array of small pins extends substantially perpendicularly from the attachment surface of a flip chip wherein the pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto. With the BGA or SLICC, the solder or other conductive ball arrangement on the flip chip must be a mirror-image of the connecting bond pads on the printed circuit board such that precise connection is made. The flip chip is bonded to the printed circuit board by reflowing the solder balls. The solder balls may also be replaced with a conductive polymer. With the PGA, the pin arrangement of the flip chip must be a mirror-image of the pin recesses on the printed circuit board. After insertion, the flip chip is generally bonded by soldering the pins into place. An under-fill encapsulant is generally disposed between the flip chip and the printed circuit board for environmental protection and to enhance the attachment of the flip chip to the printed circuit board A variation of the pin-in-recess PGA is a J-lead PGA wherein the loops of the J's are soldered to pads on the surface of the circuit board.
Wirebonding and TAB attachment generally begin with attaching a semiconductor chip to the surface of a printed circuit board with an appropriate adhesive such as an epoxy. In wirebonding, a plurality of bond wires are attached one at a time to each bond pad on the semiconductor chip and extend to a corresponding lead or trace end on the printed circuit board. The bond wires are generally attached through one of three industry-standard wirebonding techniques: ultrasonic bonding--using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding--using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding--using a combination of pressure elevated temperature and ultrasonic vibration bursts. The semiconductor chip may be oriented either face up or face down (with its active surface and bond pads either up or down with respect to the circuit board) for wire bonding, although face up orientation is more common. With TAB, ends of metal leads carried on an insulating tape such as a polyamide are respectively attached to the bond pads on the semiconductor chip and to the lead or trace ends on the printed circuit board. An encapsulant is generally used to cover the bond wires and metal tape leads to prevent contamination.
After assembly as shown in FIG. 1, a glob of encapsulant material 102 (usually epoxy or silicone or a combination thereof) is generally applied to a COB assembly 100 to surround a semiconductor chip or flip chip 104 which is attached to a substrate 106 via a plurality of electrical connections 108 which extend between a plurality of semiconductor chip bond pads 110 and a corresponding plurality of substrate bond pads 112. An under-fill encapsulant 114 is dispensed between the semiconductor chip 104 and the substrate 106. As shown in FIG. 2 the glob top materials 202 are often used to hermetically seal bare dice 204 (shown in shadow) on a printed circuit board 206 such as SIMM modules to form a COB assembly 200. The organic resins generally used in the glob top encapsulation are usually selected for low moisture permeability and low thermal coefficient of expansion to avoid exposure of the encapsulated chip to moisture or mechanical stress respectively. However, even though the chemical properties of these glob top materials have desirable properties for encapsulation, the thermal and electrical properties are often not optimal for removing heat efficiently away from the semiconductor dice or for use in high temperature areas.
Every semiconductor chip in a COB assembly generates some heat during operation. Some glob tops and package encapsulation materials serve to draw the heat away from most semiconductor chips. Indeed, one factor in choosing a package encapsulation material is its thermal dissipation properties. If the temperature of the semiconductor chip is not controlled or accommodated, system reliability problems may occur due to excess temperature rise during operation. The device/semiconductor junction temperature (the location of the heat source due to power dissipation) must be maintained below a limiting value such as 85.degree. C. The primary reason to control this temperature is that switching voltage is a sensitive function of device temperature. In addition, various failure mechanisms are thermally activated and failure rates becomes excessive above the desired temperature limit. Furthermore, it is important to control the variation in device operating temperature across all the devices in the system. This is also due to the temperature sensitivity of switching voltage since too large a variation from device to device would increase the voltage range over which switching occurs, leading to switching errors due to noise and power-supply fluctuations. Moreover, the fluctuations in temperature cause differential thermal expansions which gives rise to a fatigue process that can lead to cracks occurring in the COB assembly during burn-in or general operation.
Thus high heat producing semiconductor dice such as microprocessors may require adjustments in size of the COB assembly and will often require the addition of metal heat-dissipating fins, blocks or the like on the package. FIG. 3 illustrates a finned COB assembly 300. The finned COB assembly 300 comprises a semiconductor chip or flip chip 302 which is attached to a substrate 304 via a plurality of electrical connections 306 which extend between a plurality of semiconductor chip bond pads 308 and a corresponding plurality of substrate bond pads 310. An under-fill encapsulant 312 is dispensed between the semiconductor chip 302 and the substrate 304. A cap 314 having a plurality of heat-dissipating fins 316 is attached to an upper surface 318 of the semiconductor chip 302 with a layer of thermally conductive adhesive 320. The addition of heat-dissipating fins, blocks or the like substantially increases the cost of production for COB assemblies.
Other means for heat dissipation have also been attempted. U.S. Pat. No. 5,434,105 issued Jul. 18, 1995 to Liou relates to the use of heat spreaders attached to a semiconductor by a glob top to strengthen the heat coupling from an integrated circuit die to the lead frame wherein heat can then pass through the leads of the lead frame to the circuit board. However, the heat is not dissipated away from the circuit. Rather, the heat is conducted into the circuit board, which can still cause heat related problems. U.S. Pat. No. 5,488,254 issued Jan. 30, 1996 to Nishimura et al. and U.S. Pat. No. 5,489,801 issued Feb. 6, 1996 to Blish relate to encasing a heat slug (a piece of heat conducting material) in the encapsulation material. Although each of these patents attempts to address the problems of potential differences in the thermal coefficient of expansion between the heat slug and the encapsulation material, these attempts are never entirely successful and the adhesion interfaces between the heat slug and the encapsulation material may become separated, allowing moisture to reach and destroy the encased chip.
Changes in encapsulation materials have also been attempted to achieve high thermal conductivity, low coefficient of thermal expansion and low moisture permeability. U.S. Pat. No. 4,358,552 issued Nov. 9, 1982 to Shinohara et al. and U.S. Pat. No. 4,931,852 issued Jun. 5, 1990 to Brown et al. are examples of such attempts. However, no attempt has been entirely successful in balancing all of these desired factors or are simply too expensive.
U.S. Pat. No. 5,379,186 issued Jan. 3, 1995 to Gold et al. ("Gold") relates to a heat producing semiconductor chip attached to a substrate which uses multiple encapsulants to dissipate heat. "Gold" teaches placing a layer of encapsulant material over the semiconductor chip with a layer of thermally conductive material applied over the encapsulant material layer. "Gold" specifically teaches that the encapsulant material layer used for covering the semiconductor is a relatively poor conductor of heat (i.e. an insulative material) which is assumedly chosen for its adherence and protective properties. The thermally conductive material is applied over the encapsulant material to aid the removal of heat from the semiconductor through the insulating encapsulant material. However, this invention is inherently inefficient since the heat must be drawn from an insulative material.
Therefore, it would be advantageous to develop a technique and assembly for inexpensively forming a heat-dissipating mechanism on a semiconductor chip in combination with commercially-available, widely-practiced semiconductor device fabrication techniques.